Area and Power Efficient CMOS De-multiplexer Layout on 90nm Technology

Power dissipation in low powered devices is one of the most important considerations now days. It is very evident that hand held devices such as smart phones, calculators, tablets and laptops etc., which run on battery power, consume very low power for calculations and other operations. In this paper de-multiplexer has been designed using CMOS. In this paper the de-multiplexer has been designed with the help of 36 transistors using 90 nm CMOS technology. Two different layout design techniques have been discussed in this paper i.e.; auto generation technique and semi custom layout design. Designed layouts are compared in terms of power and area consumption. The semi customized de-multiplexer layout has shown the improvement of in power consumption and in area. Key words— De-multiplexer, CMOS, NMOS, Power dissipation, Combination logic, AND, NOT